/*
*	This is the regisiter between Decode and Execute
*	
*/

`include "definitions.v"

module Reg_DE(
	//Input Signal
	RegWriteIn,
	MemtoRegIn,
	MemWriteIn,
	ALUControlIn,
	ALUSrcIn,
	RegDstIn,
	RsIn,
	RtIn,
	RdIn,
	ShamtIn,
	SignimmIn,
	RD1In,
	RD2In,
	
	//Output Signal
	RegWriteOut,
	MemtoRegOut,
	MemWriteOut,
	ALUControlOut,
	ALUSrcOut,
	RegDstOut,
	RsOut,
	RtOut,
	RdOut,
	ShamtOut,
	SignimmOut,	
	RD1Out,
	RD2Out,
	
	//Clear Signal and Clock Signal
	CLR,
	CLK,
	
	//Conflict Dealer
	PCPlus4In,
	PCPlus4Out,
	JumpRun,
	EN
);
	input RegWriteIn,MemtoRegIn,MemWriteIn,RegDstIn,CLR,CLK,JumpRun,EN;
	input[1:0] ALUSrcIn;
	input[2:0] ALUControlIn;
	input[31:0] SignimmIn,ShamtIn,RD1In,RD2In,PCPlus4In;
	input[4:0] RsIn,RtIn,RdIn;
	
	output RegWriteOut,MemtoRegOut,MemWriteOut,RegDstOut;
	output[1:0] ALUSrcOut;
	output[2:0] ALUControlOut;
	output[31:0] SignimmOut,ShamtOut,RD1Out,RD2Out,PCPlus4Out;
	output[4:0] RsOut,RtOut,RdOut;
	
	reg RegWriteOut,MemtoRegOut,MemWriteOut,RegDstOut;
	reg[1:0] ALUSrcOut;
	reg[2:0] ALUControlOut;
	reg[31:0] SignimmOut,ShamtOut,RD1Out,RD2Out,PCPlus4Out;
	reg[4:0] RsOut,RtOut,RdOut;
	integer ClockCount;
	
	//initial 
	initial begin
		RegWriteOut	=	0;
		MemtoRegOut	=	0;
		MemWriteOut	=	0;
		RegDstOut	=	0;
		ALUSrcOut	=	0;
		ALUControlOut	=	0;
		ShamtOut	=	0;
		SignimmOut	=	0;
		RD1Out	=	0;
		RD2Out	=	0;
		RsOut	=	0;
		RtOut	=	0;
		RdOut	=	0;	
		ClockCount = 0;
		PCPlus4Out = 0;
	end
		
	//when CLR come through a posedge begin work
	always @(posedge CLK) begin
		if(EN == 1 && ClockCount == 0) begin
			if(CLR) begin
				RegWriteOut	<=	0;
				MemtoRegOut	<=	0;
				MemWriteOut	<=	0;
				RegDstOut	<=	0;
				ALUSrcOut	<=	0;
				ALUControlOut	<=	0;
				ShamtOut	<=	0;
				SignimmOut	<=	0;
				RD1Out	<=	0;
				RD2Out	<=	0;
				RsOut	<=	0;
				RtOut	<=	0;
				RdOut	<=	0;
				PCPlus4Out <= PCPlus4In;
			end
			else if(JumpRun) begin
				RegWriteOut	<=	1;
				MemtoRegOut	<=	0;
				MemWriteOut	<=	0;
				RegDstOut	<=	0;
				ALUSrcOut	<=	0;
				ALUControlOut	<=	3'b010;
				ShamtOut	<=	0;
				SignimmOut	<=	0;
				RD1Out	<=	0;
				RD2Out	<=	PCPlus4In;
				RsOut	<=	0;
				RtOut	<=	`RAREG;
				RdOut	<=	0;
				PCPlus4Out <= PCPlus4In;
			end
			else begin
				RegWriteOut	<=	RegWriteIn;
				MemtoRegOut	<=	MemtoRegIn;
				MemWriteOut	<=	MemWriteIn;
				RegDstOut	<=	RegDstIn;
				ALUSrcOut	<=	ALUSrcIn;
				ALUControlOut	<=	ALUControlIn;
				ShamtOut	<=	ShamtIn;
				SignimmOut	<=	SignimmIn;
				RD1Out		<=	RD1In;
				RD2Out		<=	RD2In;
				RsOut		<=	RsIn;
				RtOut		<=	RtIn;
				RdOut		<=	RdIn;
				PCPlus4Out <= PCPlus4In;
			end
		end
		ClockCount = (ClockCount + 1)%2;
	end
	
	/*
	always @(CLR) begin
		if(CLR) begin
			$display("time = %0d,be clear %b",$time,CLR);
			RegWriteOut	=	0;
			MemtoRegOut	=	0;
			MemWriteOut	=	0;
			RegDstOut	=	0;
			ALUSrcOut	=	0;
			ALUControlOut	=	0;
			SignimmOut	=	0;
			RD1Out	=	0;
			RD2Out	=	0;
			RsOut	=	0;
			RtOut	=	0;
			RdOut	=	0;
		end
			
	end
	*/
endmodule
